When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

Engineering Change Order or ECO is the process of inserting logic directly into the gate level netlist corresponding to a change that occurs in the rtl due to design ...

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...

This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS ...

A block of digital logic that is designed to be implemented in an ASIC or FPGA chip. A soft core is typically delivered in RTL, which is a hardware description language that defines logic at a higher ...

Formal verification tool maker OneSpin Solutions has made its 360 EC (equivalence checker) available to the FPGA market. The pushbutton EC FGPA tool helps FPGA designers ensure that RTL (register ...

The clean separation between logical and physical design is gone. RTL designers must think about implementation or suffer the consequences. True or false: ASIC design follows a very straightforward ...