EDN

How to build reliable FPGA memory interface controllers without writing your own RTL code!

As FPGA designers strive to achieve higher performance while meeting critical timing margins, one consistently vexing performance bottleneck is the memory interface. Today's more advanced FPGAs ...
EDN

SmartDV Expands Line of Memory Controller Design IP, Strengthening Its Already-Broad Portfolio of IP Products

Immediate availability of HBM2/2E, HBM3, GDDR6, LPDDR4/5, and flash. SmartDV Technologies, the proven and trusted choice for design and verification intellectual property (IP), has released a line of ...
Semiconductor Engineering

How Memory Design Optimizes System Performance

Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on ...
Electronic Design

A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!

The number of SoCs that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to DDR SDRAM interfaces such as DDR, DDR2, and DDR3 to address their low ...
Semiconductor Engineering

DRAM Simulator For Evaluation of Memory System Design Changes (ETH Zurich)

A technical paper titled “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator” was published by researchers at ETH Zurich. “We present Ramulator 2.0, a highly modular and extensible DRAM ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
Morningstar

Wolley Introduces CXL® Memory Expansion Controller for AI Workstation at FMS2025

SAN JOSE, Calif., Aug. 6, 2025 /PRNewswire/ -- Wolley Inc., a Silicon Valley high performance data interface and controller company, introduces its CXL memory expansion controller at the FMS2025.
Electronic Design

Digital Controller for DDR Memory

Powervation Ltd. announces sampling of PV3201, a new dual phase digital DC/DC controller with SVID interface. Powervation Ltd. announces sampling of PV3201, a new dual phase digital DC/DC controller ...
Design-Reuse

Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces

In today’s fast-paced SoC market, memory flexibility is no longer a luxury—it’s a competitive necessity. While DDR5 is gaining traction in high-performance systems, DDR3 and DDR4 remain dominant in ...
Geeky Gadgets

World’s First CXL Memory eXpander controller introduced by Montage Technology

Montage Technology known for its data processing and interconnect IC design has this week delivered the world’s first Compute Express Link (CXL ) Memory eXpander Controller (MXC). Created to be used ...
AppleInsider

Why Apple uses integrated memory in Apple Silicon — and why it's both good and bad

Apple's Unified Memory Architecture first brought changes to the Mac with Apple Silicon M1 chips. There are clear architectural benefits for the hardware — and it is both good and bad for consumers.