EDN

SystemVerilog Reference Verification Methodology: VMM Adoption

The larger and more complex that system-on-chip (SoC) designs grow, the more verification dominates the development process. In fact, effective design reuse puts even more pressure on the verification ...
Semiconductor Engineering

Reducing Design Risk With Testbench Acceleration

Part 1 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three ...
Electronic Design

Tool Automates Generation Of SystemVerilog Testbenches

The SystemVerilog infrastructure is built out further with Synopsys' introduction of Pioneer-NTB. This testbenchautomation tool delivers native SystemVerilog testbench generation to users of ...
Electronic Design

Find the Fastest Route to Portable Stimulus Tests with SystemVerilog

Download this article in PDF format. The Portable Stimulus Specification (PSS) is all about reusing commonly used test atoms to create new scenarios more quickly. It saves us from wasting precious ...
Semiconductor Engineering

Optimizing Testbench Acceleration Performance

Part 3 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three ...
EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. – Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...